With development of Internet technologies, various new types of services continuously develop, diverse network data types continuously emerge, and network traffic soars, thereby imposing a stricter requirement on a processing capability of a processing device. To improve the processing capability, increasingly more current processing devices begin to use a hardware processing unit (such as an FPGA or an ASIC) to accelerate some services.
In a current “CPU+FPGA”-based hardware acceleration solution, the CPU (may be considered as “a host”) is configured to execute code at a service layer (may be usually referred to as “an application layer” or “an upper layer”) and in an underlying driver. The service layer is used to generate original acceleration data, of which the process need to be accelerated, or used to receive original acceleration data scheduled from another service layer. The underlying driver is configured to cooperate with the service layer to complete work, such as parsing a scheduled instruction, data conversion, data encapsulation, or data transmission. The FPGA is configured to receive data delivered from the underlying driver, complete accelerated processing on the data, and return processed data to the service layer by using the underlying driver.
However, in this solution, acceleration for different service types needs to depend on the underlying driver. That is, specialized underlying drivers that match different service types are used for the service layer to accelerate FPGAs in corresponding functions. Therefore, in the existing technical solution, each service type that needs acceleration needs a customized underlying driver, and mobility and flexibility are poor.